The present invention relates to a program method of a flash memory device and, more particularly, to a program method of a flash memory device, which minimizes program disturbance during a program operation.
A flash memory device is a type of non-volatile memory device in which stored data is not erased when a power supply is removed.
Data can be stored in or deleted from a flash memory device through a program operation or an erase operation. The flash memory device can be classified as a NOR type or a NAND type depending on the shape of a memory cell array. The NAND flash memory device is advantageous in that it can have a high level of integration compared with the NOR flash memory device. A memory cell array of the NAND flash memory device and a program operation method are described below.
FIG. 1 is a circuit diagram illustrating a cell array of a conventional NAND flash memory device and a program operation method thereof.
Referring to FIG. 1, the cell array of the NAND flash memory device includes a plurality of memory cell blocks. Each cell block includes a plurality of cell strings (only two cell strings ST1 and ST2 are illustrated for convenience). The cell strings are respectively connected to bit lines BL1 and BL2. In more detail, the cell string ST1 has a structure in which a drain select transistor DST, a plurality of memory cells CA0 to CAn, and a source select transistor SST are connected in series. The drain select transistor DST, included in each cell string, has a drain connected to a corresponding bit line BL1, and the source select transistor SST, included in each cell string, has a source connected to a common source line CSL. The drain select transistors DST, included in the respective cell strings ST1 and ST2, have gates connected to each other, thereby forming a drain select line DSL. The source select transistors SST, included in the respective cell strings ST1 and ST2, have gates connected to each other, thereby forming a source select line SSL. The memory cells CA0 to CAn and CB0 to CBn have gates connected to each other, thereby forming word lines WL0 to WLn. The memory cells CAk and CBk, which share a word line (for example, WLk), are classified on a per page (PG) basis.
A program operation of the NAND flash memory device is executed on a per page basis. During the program operation, the drain select line DSL is supplied with a drain select voltage, for example a power supply voltage Vcc, and the source select line SSL is supplied with a ground voltage. A program voltage is applied to a selected word line (for example WLk), and a pass voltage is applied to the remaining word lines. Under the above conditions, the program operation of memory cells sharing the selected word line WLk is executed.
The threshold voltage of a memory cell is raised by the program operation, and a logical value of stored data is classified according to the changed threshold voltage of the memory cell.
Although both the memory cells CAk and CBk sharing the selected word line WLk can be programmed, under certain circumstances both the memory cells CAk and CBk sharing the selected word line WLk may not be programmed according to stored data. Different voltages are applied to bit lines connected to a corresponding string depending on which one of a to-be-programmed cell and a not-to-be-programmed cell is included in the string (a cell in which an erase state or a previous state is to be maintained). A cell that should not be programmed is hereinafter referred to as a “program-inhibited cell.”
Specifically, a ground voltage is applied to a bit line BL1 connected to the string ST1, including a to-be-programmed cell (for example, CAk). The ground voltage causes the voltage level of a channel region within the string ST1 to drop to the level of the ground voltage. Consequently, a high potential is maintained between the word line WLk and the channel region, and electrons are injected from the channel region to a floating gate of the memory cell CAk by F-N tunneling, so that the threshold voltage of the memory cell is raised. Accordingly, the program operation is executed.
A program-inhibited voltage (for example, a power supply voltage Vcc) for channel boosting is applied to a bit line BL2 connected to the string ST2, including a program-inhibited cell (for example, CBk). The power supply voltage causes the channel region within the string ST2 to be precharged to a level higher than 0V (Vcc-Vth, where V is the threshold voltage of the drain select transistor). If the channel region is precharged, the drain select transistor DST is turned off and the channel region of the string ST2, including the program-inhibited cell CBk, is floated in a precharged state because Vgs (the potential between the gate and the source) of the drain select transistor DST is not greater than the threshold voltage. If a pass voltage and a program voltage are then applied to the word lines WL0 to WLk, the voltage level of the channel region is raised higher than that of the power supply voltage due to a channel boosting phenomenon. Consequently, the potential between the word line WLk and the channel region decreases, so that F-N tunneling is not generated and the threshold voltage of the memory cell is not changed. Accordingly, the program-inhibited cell does not experience the program operation. In this case, the greater the difference between the voltage applied to the word line and the voltage of the channel region, the better the channel boosting characteristic.
A program method of storing 2-bit data or more in one memory cell has recently been developed. In order to store 2-bit data in one memory cell, threshold voltage distributions of the memory cell must be classified into four types and at least two program operations must be executed on one memory cell.
In the event that data stored in a memory cell of an erase state is defined as ‘11’, a first program operation for changing a lower bit to ‘0’ and a second program operation for changing an upper bit to ‘0’ must be executed. The first and second program operations are generally performed sequentially from the first word line WL0 to the last word line WLn.
When the program operation of the memory cells CAk and CBk, sharing a kth word line WLk, is executed according to the above method, the memory cells CB0 to CBk−1 disposed on the source select transistor (SST) side have already experienced the program operation. The cells are classified into a program state or an erase state according to stored data. A memory cell CBk+1 disposed on the drain select transistor (DST) side has not experienced the program operation, and is therefore maintained at an erase state. If a larger number of programmed cells exist on the source select transistor (SST) side, the potential between the word line and the channel region decreases due to electrons injected into the floating gate, so that a weak channel boosting phenomenon may occur. Thus, if the number of programmed cells varies for every string, channel boosting occurs with different intensities, which may result in a changed program characteristic. This phenomenon may happen not only in the program operation for storing 2-bit data, but also in a program method of storing 1-bit data.
In order to prevent this phenomenon, the program operation can be performed by using an erase area self-boosting (EASB) method of generating channel boosting only in a channel region of memory cells, which are maintained at an erase state while being placed on the drain select transistor (DST) side in the selected word line WLk. Alternatively, the program operation can be performed by using a local self-boosting (LSB) method of generating channel boosting only in a channel region of memory cells, which share the selected word line WLk by turning off the memory cells WLk−1 and WLk+1 adjacent to the selected word line WLk.
The program operation of the EASB method or the LSB method can have a good effect when memory cells disposed between the selected word line WLk and the drain select line DSL are in an erase state. However, in order to minimize an interference phenomenon in which the threshold voltage of neighboring memory cells is changed during a program operation of memory cells sharing a selected word line, the sequence of the first and second program operations or the sequence of word lines is changed. In this case, since programmed cells may exist between the selected word line WLk and the drain select line DSL, it is difficult to obtain good program characteristics even with the program operation of the EASB method or the LSB method. In particular, in the program operation of the LSB method, if a program voltage is applied, hot electrons generated from junction regions of memory cells that are turned off on both sides of the selected word line WLk are injected into the floating gate of the program-inhibited cell CBk according to the program voltage, resulting in a program disturbance phenomenon in which the threshold voltage rises.
Consequently, in order to obtain good program characteristics while preventing program disturbance, it is very important to control the occurrence of channel boosting within a string including program-inhibited cells.